1. Field of the Invention
This invention relates to processors and, more particularly, to the implementation of processor support for multiple-precision arithmetic.
2. Description of the Related Art
Securing transactions and communications against tampering, interception and unauthorized use has become a problem of increasing significance as new forms of electronic commerce and communication proliferate. For example, many businesses provide customers with Internet-based purchasing mechanisms, such as web pages via which customers may convey order and payment details. Such details often include sensitive information that might be subject to misuse if intercepted by a third party.
To provide a measure of security for sensitive data, cryptographic algorithms have been developed that may allow encryption of sensitive information before it is conveyed over an insecure channel. The information may then be decrypted and used by the receiver. However, as the performance of generally available computer technology continues to increase (e.g., due to development of faster microprocessors), less sophisticated cryptographic algorithms become increasingly vulnerable to compromise.
Cryptographic algorithms are continually evolving to meet the threat posed by new types of attacks. In particular, the use of increased key sizes may help bolster the security of a given algorithm, for example by increasing its resistance to a brute-force attack. However, computational workload can increase dramatically as key sizes increase. For example, the use of large key sizes may require an algorithm to perform arithmetic operations on operands that greatly exceed the typical operand size supported by general purpose processor hardware.